In these years, a memory card as a nonvolatile memory device mounting a NAND-type flash memory that is a rewritable nonvolatile memory is increasingly expanding own market as a memory medium of a digital camera and a mobile phone. The expansion of memory card market means an expansion of market of a host device handling the memory card. Namely, this means increase of the host device having an interface for handling the memory card.
In a different view point, many host devices tend to shift a medium for storing a program code of a microcomputer mounted on the host devices from a ROM that is a conventionally-used non-rewritable nonvolatile memory to a rewritable nonvolatile memory to shorten cycles of a development and a commercialization of product. This is because when storing the program code in the rewritable nonvolatile memory, the host device can early accept an upgrade and a correction at an occurrence of trouble, advantageously.
However, a NAND type flash memory whose unit cost of bit is presently the least expensive among the rewritable nonvolatile memories requires new techniques, for example, an error correction technique and a wear-leveling that are not necessary for a conventionally-used ROM. The wear-leveling is a process for equalizing number of rewritings of inside blocks of the NAND type flash memory.
Thus, a method for utilizing an already-equipped interface for the memory card has been recently employed without additionally mounting a technique for controlling the NAND type flash memory on the host device. In this case, by using the already-equipped interface for the memory card, the memory card is equipped directly on the host device and a program code of a microcomputer mounted on the host device is stored into the directly-equipped memory card.
Referring to FIGS. 17 to 19, a nonvolatile memory system will be explained. FIG. 17 is a block diagram of the conventional nonvolatile memory system. In the nonvolatile memory system of FIG. 17, after power-on, a host device 1702 reads a program code (a boot code) for a process executed after the power-on from a nonvolatile memory device 1701 to boot up the system.
In FIG. 17, the nonvolatile memory device 1701 is a memory card where the host device 1702 can read and write data designated with a logical address. The nonvolatile memory device 1701 is composed of a controller 1703 and a flash memory 1704. The flash memory 1704 is a nonvolatile memory having a memory cell array for storing writing-data sent from the host device 1702 in a nonvolatile manner. The controller 1703 controls the whole of the inside of the nonvolatile memory device 1701, and has an interface for the host device 1702 and an interface for the flash memory 1704.
The controller 1703 includes a processor 1705, a host IF (interface) 1706, a flash memory IF (interface) 1707, a logical-physical address conversion table 1708, and a buffer memory 1709.
The processor 1705 controls the whole of the inside of the controller 1703. The host IF 1706 controls interfaces of: data to be written and read by the host device 1702; and commands regarding the writing and reading operations. The flash memory IF 1707 controls the data writing to the flash memory 1704 and the data reading from the flash memory 1704. The logical-physical address conversion table 1708 is a table showing a correspondence between addresses used for the data writing and reading in the interface of the nonvolatile memory device 1701 and host device 1702 (hereinafter referred to as a logical address) and addresses of the flash memory 1704 (hereinafter referred to as a physical address) in order to realize a function of the wear-leveling inside the nonvolatile memory device 1701. The buffer memory 1709 is a volatile memory for: temporarily retaining data before writing the data from the host device 1702 to be written to the flash memory 1704; and temporarily retaining data read from the flash memory 1704 before reading it out to the host device 1702.
The host device 1702 includes at least a processor 1711, a main memory 1712, and a nonvolatile memory device IF (interface) 1713. The processor 1711 controls the whole inside of the host device 1702. Additionally, the processor 1711 has a function for determining a logical address used for writing data to the nonvolatile memory device 1701 and reading data from the nonvolatile memory device 1701. The main memory 1712 is a volatile memory for storing a program code read from the nonvolatile memory device 1701 and other data. The nonvolatile memory device IF 1713 controls: data used for executing the data writing or reading to the nonvolatile memory device 1701; and an interface for ordering a writing and reading operation. The nonvolatile memory device IF 1713 designates a logical address to write and read data.
Referring to FIG. 18, an operation for reading data of the program code in the conventional nonvolatile memory system will be explained. FIG. 18 is a sequence diagram showing a sequence from the power-on to the boot code reading between the host device 1702 and the nonvolatile memory device 1701.
At first, when the host device 1702 applies a voltage to the nonvolatile memory device 1701, initialization of the controller 1703 and following initialization of the nonvolatile memory device are carried out. The processor 1705 executes the initialization of the controller 1703 (controller initialization). The controller initialization is a process for: resetting a register not shown in the drawings of each part of the controller; recognizing a type of the flash memory 1704 and the number of arrays; and recognizing information related to a size and a characteristic of the nonvolatile memory device 1701 by reading data stored in a specific region of the flash memory 1704. Time required for the controller initialization is short within a few microseconds. When the controller completes the initialization, the nonvolatile memory device 1701 is able to communicate with the host device 1702 each other.
At step 1801, the host device 1702 issues an initialization command to the nonvolatile memory device 1701 via the nonvolatile memory device IF 1713. The initialization command sent from the host device 1702 is a command for initializing the nonvolatile memory device 1701. The initialization of the nonvolatile memory device 1701 is a process where the processor 1705 in the controller reads management information from the flash memory 1704 via the flash memory IF 1707 and completes the logical-physical address conversion table 1708 on the basis of the read management information. Time required for completion of the initialization of the nonvolatile memory device 1701 is approximately a few hundreds microseconds in actual time. Upon completion of the initialization of the nonvolatile memory device 1701, the host device 1702 is able to designate a logical address to the nonvolatile memory device 1701 to write and read data.
Upon reception of the initialization command issued from the host device 1702 at step 1801, the nonvolatile memory device 1701 returns a response to the host device 1702 when the controller initialization has finished, and does not return the response when the controller initialization has not finished yet. When the response to the initialization command at step 1801 has not been returned from the nonvolatile memory device 1701 yet, the host device 1702 can recognize that the nonvolatile memory device 1701 has not finished the controller initialization yet.
In order to initialize the nonvolatile memory device 1701, the host device 1702 is required to issue the initialization command to the nonvolatile memory device 1701 until the response is returned from the nonvolatile memory device 1701. Here, the host device issues the initialization command again at step 1802. When the initialization of the controller 1703 in the nonvolatile memory device 1701 has finished in receiving the initialization command at step 1802, the processor 1705 returns a response to the initialization command via the host IF 1706 at step 1803.
When the response has been returned from the nonvolatile memory device 1701 at step 1803, the host device 1702 can recognize that the initialization of the controller 1703 in the nonvolatile memory device 1701 finished and the initialization of the nonvolatile memory device 1701 has started.
The host controller 1702 that recognized the completion of the controller initialization issues a initialization completion confirmation command at step 1804, and sends the command from the nonvolatile memory device IF 1713 to the nonvolatile memory device 1701. Meanwhile, when the initialization process of the nonvolatile memory device 1701 has not finished, the processor 1705 returns a response for notifying the initialization has not finished to the host device 1702 at step 1805. During a period up to the completion of the initialization process of the nonvolatile memory device 1701, the command issuance and the response at step 1804 and step 1805 are repeated more than once.
The nonvolatile memory device 1701 creates the logical-physical address conversion table 1708, spending time (T1) of a few hundreds microseconds, and when the initialization process has finished, returns a response for notifying the completion of the initialization at step 1807 in response to a initialization completion confirmation command at step 1806 from the host device 1702.
When receiving the response for notifying the completion of the initialization at step 1807 from the nonvolatile memory device 1701, the host device 1702 recognizes that data to which a logical address is designated can be written and read to and from the nonvolatile memory device 1701. Next, the host device 1702 designates a logical address at step 1808 to read a boot code. The nonvolatile memory device 1701 outputs the boot code to the host device 1702 at step 1809.
The host device 1702 can start the nonvolatile memory system by loading the boot code read at step 1809 on the main memory 1712.
FIG. 19 shows a flowchart of a process to the host device 1702 of the nonvolatile memory device 1701, the process corresponding to the sequence diagram of FIG. 18. States from the power-on to the completion of the controller initialization are not shown in the drawing because the states are only in internal processes of the nonvolatile memory device 1701. The initialization command at step 1801 is issued from the host device 1702 to the nonvolatile memory device 1701 before the initialization of the controller. Upon completion of the controller initialization in the nonvolatile memory device 1701 after the power-on, the memory device will be in a state at judgment 1901 for waiting a command inputted from the host device 1702. The nonvolatile memory device 1701 waits at judgment 1901 until the initialization command is inputted from the host device 1702. When the initialization command is issued to the nonvolatile memory device 1701 at step 1802, the memory device judges the command as the initialization command at judgment 1901 to shift to state 1902 and returns a response of step 1803 to the initialization command of step 1802 at state 1902. In response to the initialization command from the host device 1702, the nonvolatile memory device 1701 starts the initialization process in the nonvolatile memory device 1701. The starting of the initialization process in the nonvolatile memory device 1701 and the initialization process are not shown in the drawing.
Next, shifting to judgment 1903, the memory device judges whether the initialization completion confirmation command is issued or a command other than the command is issued. In the case of the command other than the initialization completion confirmation command, the memory device waits at judgment 1903 until the initialization completion confirmation command is issued from the host device 1702.
The host device 1702 issues the initialization completion confirmation command to the nonvolatile memory device 1701 at step 1804. In response to the issuance, the nonvolatile memory device 1701 shifts the flow to judgment 1904.
When the initialization of the nonvolatile memory device 1701 has not finished at judgment 1904, the flow shifts to state 1905. The memory device returns a response indicating incompletion of the initialization at step 1805 corresponding to step 1905, and the flow returns to judgment 1903. When receiving the response indicating the incompletion of the initialization from the nonvolatile memory device 1701, the host device 1702 recognizes that the nonvolatile memory device 1701 has not been ready for the reading and writing based on the designation of logical address yet.
When the initialization of the nonvolatile memory device 1701 has finished, the flow shifts from judgment 1904 to state 1906. Upon reception of the initialization completion command at step 1806, the memory device returns a response notifying the initialization completion at step 1807 corresponding to state 1906. When receiving the response notifying the initialization completion from the nonvolatile memory device 1701, the host device 1702 recognizes that the nonvolatile memory device 101A is ready for the reading and writing based on the designation of logical address. In the flowchart shown in FIG. 19, the initialization has entirely finished, and after the completion of the initialization, the host device 1702 issues a boot code reading command at step 1808 and reads a boot code at step 1809 to start the system.    Patent document 1: Japanese Unexamined Patent Publication No. S62-221034